Hi there,
This week I want to talk about something that doesn't get nearly enough airtime in the quantum computing conversation: the manufacturing side of building superconducting qubit processors. Not the physics. Not QEC or the algorithms. The part where you've spent months designing a chip, run it through the fab, and then find out your qubit frequencies are off. Again.
Qubit frequency targeting is one of the most persistent headaches in superconducting quantum computing.
Luckily many teams are working on a range of post-processing techniques to tune qubit frequencies after the fabrication is done. The Chalmers team just published one of the most thorough characterizations of such a technique, and the approach and results are worth spending some time on.
Why is frequency targeting still such a problem?
When a chip comes out of the fab, the Josephson junctions almost never sit at exactly the resistance you designed for. Each junction is a few nanometers of aluminum oxide grown between aluminum electrodes by thermal oxidation, and that oxidation process is notoriously sensitive. Even small variations in barrier thickness shift the Josephson energy E_J, which shifts the qubit frequency.
On a multi-qubit chip, this means some qubits end up too close in frequency to their neighbors. That causes crosstalk, leakage errors, and calibration complexity that compounds as you add more qubits.
What is the Chalmers team doing ?
The Chalmers team characterizes post-fabrication electrical tuning: applying voltage pulses directly to the junctions at room temperature after the chip is already fabricated. When you stress the AlOx barrier with a field in the 750 to 1050 mV range, oxygen ions within the oxide seem to redistribute irreversibly. This increases the tunnel resistance R_N. Via the Ambegaokar-Baratoff relation, a higher R_N means lower E_J, which lowers the qubit frequency.
This is not thermal annealing. The estimated local temperature rise at the junction is only around 4 K, nowhere near recrystallization temperatures. The electric field is doing the work. And the whole procedure runs at room temperature with a probe station and a voltage source.
Does it actually work?
On two 8-qubit test chips, they demonstrated resistance increases of nearly 270%, with qubit frequencies shifting as predicted. Qubit coherence survives the procedure. The paper reports qubit quality factors between 1 and 1.5 million before and after tuning.
The current frequency precision is around 11.3 MHz, bounded by how well you can predict the resistance drift that occurs at room temperature in the window between tuning and cooldown. Once the chip is cold, that drift stops entirely.
What would this look like in a real fab workflow at scale?
This is the part I keep thinking about. The basic sequence is: measure junction resistances across the full wafer at room temperature, compute the required correction for each qubit, apply targeted voltage pulses, wait for the fast initial drift to settle into a slower regime, then cool down.
But each of those steps has real engineering requirements when you're doing this at scale:
First, you need electrical access to individual junctions at the probe stage. That means dedicated contact pads for each junction, or at least for each qubit, designed into the chip layout from the start. This is not a huge ask but it has to be planned for.
Second, you need per-wafer calibration. The paper is explicit about this: the breakdown voltage varies with junction geometry and oxide thickness, and the manipulation voltage range needs to be characterized for each new process or wafer batch. For a fab running multiple process variants, that means maintaining a calibration library. Not complicated, but it is real work that needs to sit somewhere in the production flow.
Third, the timing between tuning and cooldown matters. The resistance drifts logarithmically at room temperature after tuning, fast at first and then slowing down. The strategy is to wait for that initial fast phase to pass before cooling, so your relaxation model can predict the final state more accurately.
Fourth, and this is the real open question for scale: the 11 MHz precision bound. At that spec, if your frequency targeting requirement is tighter, you are looking at an iteration loop. Cool down, measure qubit frequencies at base temperature, warm up, retune, cool down again. Each cooldown is hours/days. For a production environment that is expensive. Getting the precision to 5 MHz or below is probably what unlocks this as a true manufacturing tool rather than a lab technique.
The technique is genuinely compelling though. It is fully electrical. No laser optics, no SEM, no vacuum. Every semiconductor fab already has probe stations and voltage sources. If the precision problem is solved, the integration path into an existing fab line is straightforward in a way that laser annealing simply is not.
Until next time,
References
Christian Križan, Maurizio Toselli et al. Electrical post-fabrication tuning of aluminum Josephson junctions at room temperature
Thumbnail: MIT Lincoln Laboratory